A current mirror is an electronic circuit in which a current that is generated acts as a master current, such that one or more slave currents are provided that are each proportional to the master current. As an example, a current mirror can include a master transistor that forms a current path for the master current and one or more additional slave transistors that form respective current paths for the slave currents. To provide the slave currents at respective magnitudes that are proportional to the master current, the master transistor and the additional slave transistors can be biased by a common bias voltage. Variations in magnitude between the slave currents and the master current can result based on a mismatch in size between the master transistor and the one or more slave transistors. As a result of the versatility of providing one or more currents proportional to a predetermined current, current mirrors can be implemented in any of a variety of circuit applications.
FIG. 1 illustrates an example of a typical current mirror system 10. The current mirror system 10 can be implemented in any of a variety of applications to provide at least one slave current IS that is proportional to a master current IM. The current mirror system 10 includes a master circuit 12. As an example, the master circuit 12 can include a transistor, such as a bipolar junction transistor (BJT), and a bias resistor that collectively provide a current path for the current IM between a positive rail voltage VCC and a negative rail voltage, demonstrated in the example of FIG. 1 as ground. The current IM can be generated from a current source 14, such that the current IM can be controlled to have a predetermined magnitude. In the example of FIG. 1, the current source 14 provides the current IM to ground, such that the BJT transistor in the master circuit 12 can be configured as a PNP-type BJT. However, it is to be understood that the example of FIG. 1 is not limited to the use of PNP-type BJTs, such that the current source 14 could be configured to draw the current IM from the positive rail voltage VCC to provide the current to a collector of an NPN-type BJT in the master circuit 12.
The current mirror system 10 also includes a slave circuit 16. Similar to the master circuit 12, the slave circuit 16 can likewise include one or more transistors, such as BJTs, and a respective one or more bias resistors that each collectively provide a current path for each of the respective slave currents IS. Each of the slave currents IS can have a magnitude that is equal to the master current IM, or can have a magnitude that is proportional to the master current IM. It is to be understood that the proportionality of each of the slave currents IS relative to the master current IM can be separate with respect to each other, such that slave currents IS can have magnitudes that are not equal with respect to each other. As an example, similar to the master circuit 12, the BJT transistors of the slave circuit 16 can each be configured as PNP-type BJTs. As a result, the current paths of each of the slave currents IS can begin from the positive rail voltage VCC, and each of the slave currents IS can be provided to any of a variety of loads.
To achieve the proportionality between the slave currents IS and the master current IM, the BJTs of the master circuit 12 and the slave circuit 16 can have respective base terminals that are coupled together and are biased by a common bias voltage (e.g., approximately 0 volts). As such, the master circuit 12 can include one or more transistors that are configured to set the bias voltage for the respective master circuit 12 and slave circuit 16. Thus, in the example of FIG. 1, the base terminals of the respective BJTs of the master circuit 12 and the slave circuit 16 are coupled together, as demonstrated at 18.
As an example, the one or more transistors can include a beta helper transistor. Specifically, the beta helper transistor can be configured in a feedback arrangement with the transistor of the master circuit 12. For example, a collector of the transistor of the master circuit 12 can be coupled to a base of the beta helper transistor and an emitter of the beta helper transistor can be coupled to the base of the transistor of the master circuit 12 and the transistors of the slave circuit 16. As a result, the beta helper transistor can set a common bias voltage for the master circuit 12 and the slave circuit 16 for the generation of the slave currents IS proportional to the master current IM.
In the example of FIG. 1, the current mirror system 10 also includes a compensation capacitor CCMP. The compensation capacitor CCMP can be configured to stabilize the master current IM, and thus the slave currents IS. For example, transient effects on the master current IM can result in undesired oscillation of the master current IM, and thus the slave currents IS. As a result, the compensation capacitor CCMP is configured to substantially mitigate the transient effects and thus maintain the master current IM and respective slave currents IS as substantially constant based on an amount of charge stored therein.
In many applications of the current mirror system 10, it may be necessary to activate and deactivate the current mirror system 10. Specifically, it may be necessary to deactivate the supply of the slave currents IS to all of the respective loads to which they are provided. As a result, the current mirror system 10 can include a manner in which to activate and deactivate the current mirror system 10, such that the slave currents IS are respectively provided and deactivated (i.e., reduced to a magnitude of zero).
In the example of FIG. 1, the current mirror system 10 includes a switch circuit 20 that is arranged in parallel with the master circuit 12 and the compensation capacitor CCMP. The switch circuit 20 can be configured to divert the master current IM from the master circuit 12 through the switch circuit 20 in response to an activation signal, thus preventing the master current IM from being mirrored through the slave circuit 16. However, such an arrangement typically changes a respective voltage across the compensation capacitor CCMP, which may be required to hold a specific amount of charge to prevent unintended current flow through the master circuit 12 during deactivation of the current mirror system 10. As a result, upon activating the current mirror system 10, such that the master current IM is again provided through the master circuit 12, the compensation capacitor CCMP may need to build charge in response to the change in voltage across it. Accordingly, the slew resulting from the building of charge in activating the current mirror system 10 results in an increase of the time that it takes to activate the current mirror system 10.
A smaller compensation capacitor CCMP could be implemented in the current mirror system 10, such that the slew rate at activation of the current mirror system 10 can be mitigated. However, a smaller compensation capacitor CCMP is substantially less effective at stabilizing the master current IM. Additional circuit devices could be included in the switch circuit 20 to increase a voltage-drop across the parallel path of the switch circuit 20. However, it may be very difficult to provide the correct voltage-drop magnitudes across the additional circuit devices to prevent slew of the compensation capacitor CCMP, and additional devices can result in a larger physical size of the current mirror system 10.
Another example of a manner for activation and deactivation of the slave currents IS is described with reference to the example of FIG. 2. FIG. 2 illustrates another example of a typical current mirror system 30. In the example of FIG. 2, like reference numbers are used to demonstrate the components of the current mirror system 30 having substantially the same function as that described above with reference to the current mirror system 10 in the example of FIG. 1.
In the example of FIG. 2, the current mirror system 30 includes a switch circuit 32 that interconnects the master circuit 12 and the slave circuit 16. The switch circuit 32 is thus configured to connect and disconnect the slave circuit 16 from the master circuit 12. Specifically, one or more switches can decouple the bases of the transistors of the slave circuit 16 from the beta helper transistor in the master circuit 12 and instead couple the respective bases to an opposite bias voltage (e.g., the positive rail voltage VCC). As a result, the bias voltage is removed from the slave circuit 16, resulting in the transistors within the slave circuit 16 being switched to a cutoff mode. However, the transistors that constitute the current paths in the slave circuit 16 may be sized large to provide large amounts of the slave current IS. As a result, one or more of the transistors in the slave circuit 16 may include a significant amount of parasitic base capacitance from being coupled to the opposite bias voltage. As such, the activation time of the current mirror system 10 can be significantly increased for the slave currents IS based on an RC delay resulting from the base capacitance of the transistors of the slave circuit 16. Such a delay in activation time can be mitigated by including a large switch in the switch circuit 32 for disconnecting the bases of the slave transistors in the slave circuit 16. However, similar to as described above, a large switch can result in a larger physical size of the current mirror system 10. Furthermore, the slave currents IS can still have activation times that vary relative to each other.